The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits, and methods of manufacturing the same.
Integrated circuits are generally created by forming an array of electronic devices (i.e. transistors, diodes, resistors, capacitors, etc.) and interconnect wiring on a semiconductor substrate. Very generally, semiconductor devices and gates are formed in a first layer during front-end of the line (FEOL) processing, followed by formation of interconnect wiring in a second layer by back-end of the line (BEOL) processes. These first and second layers can each contain multiple layers of dielectric material which electrically isolate the devices and interconnecting wires. Multiple integrated circuits (ICs) can be produced simultaneously on a semiconductor wafer, and ‘singulated’ into individual chips by dicing. Integrated circuit technology has steadily advanced to increase the number and density of devices on a chip by decreasing the feature size. However, further advances are limited in such a 2-dimensional (2D) array as the feature size approaches the atomic scale.
An alternative approach to improve capabilities of an integrated circuit is to stack and integrate separately built 2D components, for example, a memory component bonded and integrated to a logic component, to form a three-dimensional integrated circuit (3D IC). The separate components are generally planar, each having a substrate layer and typically having devices and wiring formed in dielectric layers on one surface of the substrate. The exposed substrate surface may be considered the ‘back’ or the bottom, and the exposed surface of the wiring layer may be considered the ‘face’ or top of the component. A 3D IC can be created by bonding two or more of such components, which may be oriented ‘face to face’, meaning bonding the device side of each together, or ‘face to back’, or even ‘back to back’, i.e. substrate to substrate.
Bonding can be achieved by C4 adhesion, or more integrally, such as by forming an oxide-to-oxide bond that fuses silicon dioxide materials from two components. Another technique, is to fuse metal structures within the separate components, for example by contacting opposing copper pads and processing to grow copper grains across the original interface between the opposing copper pads. Regardless whether the components are ‘face to face’ or ‘face to back’, the bonded structure includes at least one BEOL layer between two semiconductor substrate layers. To enable interconnection to wiring in such an embedded BEOL layer, it is known to form a conductive structure through one of the semiconductor substrate layers, usually after thinning the substrate. Such a conductive structure is known as a ‘through silicon via’ (TSV). The semiconductor substrate can be thinned by grinding and chemical mechanical polishing (CMP). In contrast to a semiconductor wafer of a typical integrated circuit that may be on the order of one millimeter thick or, for example, about 785 um thick, thinning may substantially reduce the substrate thickness to only about 10 microns, or between 5 and 25 microns, which is similar to the thickness of the BEOL layer.
3D ICs can be formed by bonding chips before or after dicing, i.e., die to die, die to wafer, or wafer to wafer. Greater throughput would be achieved by forming 3D ICs at the wafer scale, but subsequently singulating the composite can damage many of the dice, reducing the yield. During dicing, forces applied to the chip edge via friction with the dicing blade can result in local chip edge damage such as small cracks or delaminations. When a chip is subsequently mounted in a package, thermal expansion mismatch between packaging materials and the chip can result in long range stress fields that can drive dicing flaws into the active area of the chip resulting in circuit failure. This problem can be addressed in typical 2D integrated circuits by forming a narrow region that is continuous around the periphery the chip such as a metal wall to block propagation of a crack, i.e., a crack stop. Such structure can be included at all FEOL and BEOL levels so it extends continuously through all the layers formed on the substrate such that a crack cannot circumvent the crack stop along an alternate parallel weaker path.
There is currently no good technique for including such a crack stop structure across the bonded interface between components in a 3D IC. This interface may be weakly bonded or formed within low toughness brittle materials, making the bonded region especially susceptible to damage during dicing. Also, the substrate layer of at least one of the bonded components in a 3D structure is typically thinned for purposes of 3D integration. The thinning process can produce dislocations or other flaws in the substrate, in addition to damage caused by dicing. Edge damage to a bonded region or to a thinned substrate layer may propagate as cracks into the electrically active region and cause failure of the 3D structure. A 3D IC that is more resistant to damage during dicing is needed.